• Digital Circuit Design Engineer

    Pay negotiation (competitive wage level of the industry)

    Number of recruits: 2 查看详情

    Job description:

    1. Evaluate and integrate IP to SOC system level, including clock, reset design, etc.

    2. Responsible for the function definition and RTL design of key modules of SOC chips;

    3. Chip architecture design, integration, etc.

    4. Assist in SoC chip testing, debugging and application.

    Job requirements:

    1. Bachelor's degree or above in related disciplines such as electronic engineering, Microelectronics or integrated circuits, and excellent fresh graduates are available;

    2. Experience in SOC design and development is preferred.

    3. Understanding the overall process of integrated circuit manufacturing takes precedence;

    4. Familiar with SOC chip system architecture/front-end design, good at Chip level Integration first;

    5. Familiarity with synthesis of IC flow is preferred;

    6. Experience in R&D of large scale SOC chip design projects is preferred.

    7. Familiarity with security algorithms and low power design are preferred;

    8. Strong logic analysis and independent problem solving ability;

    Location: 19th floor, Shandong Aerospace artificial intelligence security chip research institute, 933 Shuntai North Road, Jinan high tech Zone, Shandong Province

  • Digital circuit verification engineer

    Pay negotiation (competitive wage level of the industry)

    Number of recruits: 2 查看详情

    Job description:

    1. Be familiar with UVM verification methodology and be able to build UVM verification code platform;

    2. Responsible for SoC sub module verification, writing verification plan and verification report;

    3. Responsible for the construction of chip verification environment and chip level pre SIM and post SIM verification;

    4. Be responsible for the integration and verification of third-party IP modules;

    5. Responsible for chip level performance verification and exception verification.

    Job requirements:

    1. Bachelor degree or above in electronic engineering, microelectronics or integrated circuit and other related majors, excellent fresh graduates can be;

    2. Experience in digital integrated circuit design, SoC / ASIC design / verification is preferred;

    3. Familiar with VCs, NC Verilog and other design verification tools;

    4. Familiar with system Verilog language and UVM verification methodology;

    5. Familiar with Linux and scripting language, such as Perl, python, etc. is preferred;

    6. Strong logical analysis and independent problem solving ability;

    7. Be proactive, good at communication and dare to take responsibility.

    Location: 19th floor, Shandong Aerospace artificial intelligence security chip research institute, 933 Shuntai North Road, Jinan high tech Zone, Shandong Province

     

  • FAE Application Engineer

    Pay negotiation (competitive wage level of the industry)

    Recruitment: 2 查看详情

    Job description:

    1. Responsible for the design penetration of new products, understanding customer needs, and completing Design in and Design win;

    2. Solve client problems in time and provide on-site technical support;

    3. Learn and understand customer applications and make new product revision suggestions.

    Job requirements:

    1Bachelor's degree or above, electronic information and computer related specialties, excellent fresh graduates are available;

    2. Familiarity with smart card protocols such as ISO7816 and ISO14443 is preferred.

    3. Familiarity with C or C#language or C++ language is preferred;

    4. Programming basics are preferred;

     

    5. Be brave to work under pressure and setbacks, and be able to adapt to travel abroad;

    6. Strong logical thinking ability, language expression ability and text organization ability.

    Location: 19th floor, Shandong Aerospace artificial intelligence security chip research institute, 933 Shuntai North Road, Jinan high tech Zone, Shandong Province

     

  • Digital Backend Design Engineer

    Pay negotiation (competitive wage level of the industry)

    Number of recruits: 2 查看详情

    Job description:

    1. Understand the chip architecture and circuit structure together with the logical design team to complete the physical design process;

    2. Engage in physical synthesis, power planning and clock design;

    3. Docking outsourcing companies complete layout and wiring, time series analysis and convergence, IR/EM/Noise analysis, physical validation, etc., and complete signoff requirements.

    Job requirements:

    1. Familiarity with SDC constraints, P&R flow, STA signoff, physical verification tools;

    2. Familiar with industry EDA tools, preferred with experience in interface IP (PCIe/DDR) integration;

    3. Skilled in scripting languages such as Shell/TCL/Perl/Python;

    4. Flow experience of process node chips at or below 40 nm.

    Location: 19th floor, Shandong Aerospace artificial intelligence security chip research institute, 933 Shuntai North Road, Jinan high tech Zone, Shandong Province

Recruitment process and interview instructions

(1) Resume delivery

The candidate can apply for the position through the recruitment website and the official website of the company

Delivery address: bixiaoxiao@holichip.com

(2) Resume screening

After the preliminary screening of the submitted resume by human resources, if the resume meets the post requirements, it will contact the candidate for interview

(3) Double interview

HR qualification interview, professional interview, background investigation, offer